1. Field of the Invention
Embodiments of the invention generally relate to electronics, and more particularly, to high speed data links for integrated circuit devices.
2. Description of the Related Art
Reliable high speed serial links between integrated circuit devices can be difficult to implement with rising data rates. State of the art serial links exceed 10 gigabits per second (Gbps). In receivers, electrostatic discharge (ESD) protection, input pad and packaging requirements adversely affect the signal integrity of device-to-device communication links by adding parasitic capacitance to inputs.
Some receivers of serial communication systems use relatively limited analog processing. For example, in these receivers, often only a high-speed analog-to-digital converter (ADC) is present for the analog section. Other functions can be performed digitally, such as equalization and clock and data recovery (CDR). An absence of front-end analog equalization imposes relatively severe demands on the signal integrity of the receiver.
Return loss (RL) at the IC-package interface and insertion loss (IL) from frequency dependent attenuation of on-chip interconnects are two factors affecting the signal integrity of an input data signal.
Discontinuities and impedance mismatches can occur at interfaces between an integrated circuit (IC) and its package. A transmission channel can include, for example, board traces, backplane traces, and/or short lengths of cable. To minimize the magnitude of reflections in the channel (return loss), ideally the input impedance of the receiver (Zin) should be matched complex conjugate of the characteristic impedance (Z0) of the transmission line, e.g., real(Zin)=Z0 and Img(Zin)=0. Mismatches in impedance cause some of the signal power to be reflected back into the transmission channel, which typically results in increased jitter. This increased signal jitter directly translates to a reduction in the overall performance of the link.
The larger the impedance discontinuity, the greater the degradation in the quality of the input serial data signal. In the frequency domain, the effect of these discontinuities can be seen as sharp notches in the channel response and can be somewhat reduced using nonlinear equalizers. To minimize the signal degradation due to poor RL, a receiver should be properly matched to the impedance of the transmission line.
The frequency-dependent insertion loss of on-chip interconnects can cause inter-symbol interference (ISI). By flattening the overall amplitude response of the receive path, a linear equalizer can partially compensate for insertion loss.
A power efficient way to implement linear equalization is by only using passive reactive components. A typical goal of an input circuit is to present a constant, real 50 ohm (Ω) termination resistance to the external transmission line (assuming the transmission line has a 50 ohm characteristic impedance), and to provide a frequency dependent voltage gain that compensates for losses. In real systems, a more realistic requirement is to create a 50Ω termination from DC up to about ¾ of the baud rate, where most of the digital signal energy is concentrated. Similarly, insertion loss is also usually of interest up to ¾ of the baud rate.
FIG. 3 illustrates a representative power spectrum of serial non-return-to-zero (NRZ) data. Frequency is expressed along a horizontal axis. Power is expressed along a vertical axis. The majority of the signal energy is contained up to about 75% of the baud rate f0. Thus, in the case of multi-gigabit transmission systems, a significant amount of signal energy can be reflected if the input impedance is not relatively well matched at high frequencies.
FIG. 1 illustrates an example of a conventional input circuit for an integrated circuit assembly including an on-chip pad 102, an electrostatic discharge (ESD) protection circuit 104, a resistive termination Rt, and a receiver (RX). Those components are also sources of parasitic capacitance that can be modeled by two separate capacitors C1, C2. Resistance Rp models on-chip routing resistance.
As the link rate of serial data transceivers increases, parasitic on-chip capacitance and resistance can severely degrade the quality of the input signal when it reaches the on-chip receiver circuitry (for example, ADC, sampler, amplifier, etc.).
Conventional solutions to discontinuities and impedance mismatches include, for example, broadband matching networks, improving insertion loss, or combinations of both. U.S. Pat. No. 7,005,939 to Zerbe, et al, describes using a series inductive element to isolate the C1 and C2 capacitance and to prevent the capacitance from summing. The series inductance is placed between the ESD protection circuit and the termination resistor Rt, thereby effectively reducing the capacitance present at the pad. U.S. Pat. No. 7,265,433 to Pillai, et al, discloses a T-coil inserted between the ESD protection circuit and the termination resistor Rt. The receiver is connected at the T-junction of the T-coil. Such a configuration transforms capacitance C2 into a constant real 50Ω termination resistance in parallel with capacitance C1. While Pillai's technique nulls the C2 reactance across frequency, the C1 reactance remains present at the pad.
FIG. 2 illustrates another conventional example of a serial data link and a receiver. A transmitter 202 drives a transmission channel 204, such as board traces, backplane traces, and/or cables. A receiver chip 206 has a termination resistor Rt, a primary ESD protection circuit 208, a current-limiting resistor R 210, a secondary ESD protection circuit 212 and a receiver circuit RX 214. The ESD protection is provided by two separate circuits (primary 208 and secondary 212).
The primary ESD protection circuit 208 is typically connected directly to the input pad 102 (FIG. 1) and typically includes a diode placed between the signal line and ground, and another diode placed between the signal line and the local voltage supply rail. In advanced sub-micron CMOS technologies, secondary protection in the form of a voltage clamp (secondary ESD protection circuit 212) is commonly used at the receiver circuit RX 214 input in order to limit the voltage at the MOSFET transistors gates in the receiver circuit RX 214.
A drawback of the technique illustrated in FIG. 2 is that the total capacitance associated with the primary ESD protection circuit 208 and the secondary ESD protection circuit 212 can be relatively large. In the case of multi-gigabit communication links, the capacitance at the input of the receiver circuit RX 214 can be a limiting factor in system performance. As data rates increase with each successive generation of technology, the problems associated with input capacitance become more acute. The parasitic capacitance at the receiver chip input due to signal trace routing and ESD protection circuitry typically render the input impedance of the receiver frequency dependent. At low frequencies, the input impedance is about equal to the DC resistance of the termination resistor Rt. At higher frequencies, the impedance is lowered due to both the ESD protection capacitance and the pad capacitance. Thus, the impedance mismatch at the input increases with increasing frequency.
The current-limiting resistor R 210 disposed between the primary ESD protection circuit 208 and the secondary ESD protection circuit reduces the overall size of the ESD protection circuits. The use of the current-limiting resistor R 210 permits the physical size of the secondary ESD protection circuit 212 to be reduced since it does not have to be designed to carry the full ESD discharge current. Thus, there is a tradeoff between the capacitance added by the secondary ESD protection circuit 212 and the size of the current-limiting resistor R 210. The secondary protection can be made smaller, but the resistor must be made larger to limit the current (and vice versa).
FIG. 4 illustrates a lumped-element model of the circuit described earlier in connection with FIG. 2. The primary ESD protection circuit 208 and the parasitic pad capacitance are represented as a single capacitance Cp1 402. The secondary ESD protection circuit 212 and input capacitance of the receiver circuit RX 214 is lumped into another capacitance Cp2 404. Modeled resistance Rp 406 represents the sum of both the parasitic resistance of the routing trace and explicitly added current-limiting resistance R 210 which can be upwards of 200Ω depending on the technology and design requirements. As illustrated in FIG. 4, the termination resistor Rt is placed on the transmission channel side of the modeled resistance Rp to avoid a voltage division with the modeled resistance Rp. In the illustrated ESD configuration, if the termination resistance Rt were to be placed in parallel with Cp2 404, it would create a voltage divider with R−p (Rt/(Rt+Rp).
Along with the degradation caused by impedance mismatches from the ESD protection circuits and parasitic capacitances at high frequency, attenuation (insertion loss) of the input signal on-chip also reduces the overall performance of the link. The quality of the input serial data signal is further degraded by attenuation associated with the on-chip parasitic capacitance Cp2 and modeled resistance Rp. The modeled resistance Rp and parasitic capacitance Cp2 form a low-pass filter, which decreases the magnitude of the input signal as seen by the receiver circuitry, which increases inter-symbol interference (ISI). When the bandwidth of the input signal is limited by the current-limiting resistance Rp, trace resistances, and the parasitic capacitances, then the input signal will be significantly attenuated and distorted by the time it reaches the input of the receiver circuit RX 214. Greater ESD protection uses relatively larger devices, which increases the amounts of parasitic capacitances Cp1 402 and Cp2 404, while the addition of secondary protection in advanced CMOS technologies typically uses secondary voltage clamps 212 and a current-limiting resistor R. Thus, a tradeoff exists between the level of ESD protection and operating performance.